MZ@ !L!This program cannot be run in DOS mode. $ѼԺԺ-ԺRichPEd”Y\" 0@ ``A\0P@$0%P8.text h.rdata @H.datahb ^@.pdata$l@HPAGEFWt@INIT0 b.rsrc@@B.relocP@BH(LD$XHmHH rIP@AǀHqHhHmH`IHmA@mA@d%8p%5p%q%q%qmpA`fA@HA@afAǀfA@QA@SA@WfA@ZA@0A@A@YAǀAƀtH ==t H H(̅tttøfA@A@3@SH Hjt H 2=H H(f2ft H =H [HHHD$xHD$0HD$pHD$(LL$ E3HH̰H\$WHPd$pH3HH nDBXeAHH;H}nHH Ȼc<L\nLL$p3H;H>nHT$pH »-<DD$p3H nL`nH nH%nmnmnD mHmmD mDmL$HD$@HT$8L$0D$(HT$ HmHm mH Bm;2H\$`HP_H\$Hl$Ht$WATAUAVAWH@B3BHLDu<tH k&;CrH ;3ҍJB33mHH {HD:EV33 mH۹H HD:DsRHʅA+ t kH AE3HA@yB@-iH@-mZl@8-i=iD9=kDB=k;=kD@DG5kA+DNiEƋQiAD CiH@l$0Dd$(D$ @t mHku@2t@E@2AEtaH I9A3@8-h@8-ht @-h*H ֶ9f%lWnlibfCA@H 8H H h8HAXBHjLI38L\$@AI[0Ik8Is@IA_A^A]A\_H\$H|$UHl$HHHHuHu H nI83HMAHeHiHiDML;r H  7L1iIML,iDLiH 6H\$Hl$Ht$WH HcH~D3ۍ{+H 6%}ȃuHt H 6HH;|H ˷H\$0Hl$8Ht$@H _r6LD$LL$ SVWH 3HBH=H Gx4HZHHLL$X346xHH;wu@<3@<3HtH _^[@SUVWHHH3H$H$AL$ IHL$0H+AHT$ HL$0^3IIB<uHHL$0C3DHL$0H33HHL$0)H$H34HĨ_^][H\$Hl$Ht$ WE3HLH HED8 t HLD8uAE+HAA@B<=u?A@BȀ=AD+A؃u=tu=tD+AAEALT$B =]/u??+u>6A<wA<wA< w@A IƃrDT$D$AʊT$ ȋLj (A€ Ȋˆ /NJL$? Ȉ /A;? T$DT$HT$B =/u?7+u>.A<wA<wA< wxQ@tL AHD;rD$DT$T$A ȋLj (uAA ҈/Nj H\$Hl$ Ht$(_HHXHpHxLp AWH MLHIIB<uA90IAt\BAAA™4@IgHHtCDHOH.HcxII3A6LABA+pgHHu&HODH4yHgH\$0Ht$8H|$@Lt$HH A_HHXHhHpHx AVH03LHHuH$`H3bH$Hp_H\$Hl$Ht$WH H5OAH3AA譕\$`AE3$FD$PȉFDNLNˉ^ NH\$0A# ~NA#͉n Hl$8 ЋD$XȉF$AA0ωV~(DN0Ht$@H _H\$Ht$WH H5fNAH3HANAHfFf MA# A#M ЉVKA# Ћ%  ЉV MA# A#M ЉV MA# A#jMLCH HN ЉVDd{H*uF=+Mtω~H\$00Ht$8H _HHXHhHpHx ATAVAWH@HH3H$0L5M@I3A謓AF3AC@t=Ju AF AFfA^AA^HnC4IFA0fA^A^fA^ lLA# A#VL AV FLA# A#0L AV@dsIi L RMIv0LIHqAoHHt18tHH+uH¾ H#HtHH+ H ΅M~1LL dJLILMHILMt)HA8tLH+uHH#Ht LL+΅LMII2M=~H A\$ EH$03ؑEHL$03ɑHL$ AH$0ALD$2fD$00bAH$03DL$ O$>ILH0LMt*HA8$tLH+uHH#Ht LL+΅LL$0LHMIIMLO<&IHM]HA83LH+u&Iv0LHHHt5׽8tHH+uHHс HtHH+ H HIL{1B L JIv0L+IHHýHt18tHH+uH¾ H#HtHH+ H L JM~1LԚLHLIIMILMt)HA8tLH+uHH#Ht LL+΅HHIILH2LO<&IOLMt)HA8tLH+uHH#Ht LL+΅HHIILYHLO<&ILMt)HA8tLH+uHH#Ht LL+΅HHIILHLO<&IHMt.HA8tLH+uHH#HtHH+H΅HIL{MUIv0L kEHL 4HýHt18tHH+uH¾ H#HtHH+ H ΅M~1LL ELILMHILMt)HA8tLH+uHH#Ht LL+΅HIII2L9AD!L 0HO<&ILaIHVLMt)HA8tLH+uHH#Ht LL+L GHHIIIHLLO<&ILMt)HA8tLH+uHH#Ht LL+΅HHIILڗHLO<&ILMt)HA8tLH+uHH#Ht LL+΅HIIILO<&HIL MCL.9LMt)HA8tLH+uHH#Ht LL+΅HHIILHLO<&ILMt)HA8tLH+uHH#Ht LL+΅HHIILHLO<&ILMt)HA8tLH+uHH#Ht LL+΅HHIILsHLO<&I1LMt)HA8tLH+uHH#Ht LL+΅L BHHIIL4HLO<&ILMt)HA8tLH+uHH#Ht LL+΅HHIILHLO<&IzLMt)HA8tLH+uHH#Ht LL+΅L ^AHHIILHLO<&ILMt)HA8tLH+uHH#Ht LL+΅L @HHIILnHLO<&ILMt)HA8tLH+uHH#Ht LL+΅L @HHIIL/HLO<&I]LMt)HA8tLH+uHH#Ht LL+΅HHIIILLO<&ILMt)HA8tLH+uHH#Ht LL+΅HHIIILLO<&ILMt)HA8tLH+uHH#Ht LL+΅HHIIILLO<&IULMt)HA8tLH+uHH#Ht LL+΅HHIIILLIO<&ILMt)HA8tLH+uHH#Ht LL+΅HHIIILLO<&ILMt)HA8tLH+uHH#Ht LL+΅LMIIM9!>u[O$>HILEHMt/HA8$tLH+uHH#HtHH+H΅HIILIWH u`AOAANH$0H3 L$@I[ Ik(Is0I{8IA_A^A\@SH H;@3HAӆfFAE3DC ?A# A#? fDC ЉS ?A# A#? ЉS ?A# A#n? A@0SH [@SH H?3HAK3CAHCf@ <A# A#< ЉS >A# A#> ЉS >A# A#> и0SH [@SUVWAVHpH6H3HD$h3IH!\$ ILtT3HL$(DB?8΋ILL$ +LD$(t7LD$(L+HB+uHut0;rHH z HL$hH3C HpA^_^][LL$ L<Ho3H\$Ht$WH DHAA?E#HAE+HH{3AHAsRE^AHBJ B  ȉ HRAuHKH3HDB8EA AHBJ B  ȉ HRAu֋HKCPH׋CCTAHSBJ B  ȉ HRAuCH\$0Ht$8H _@SH 3HDBX`C#EgC CܺCvT2H [HL$SUVWATAUAVAWH8DQHDIDA AA3A#‹ A3Dc$xj׉T$ȋSAA3‰$ADD$ #DL$A3DT$AVDCADD$ 3 #A3AEp $DK DD$3ADA#3AEνDSDDT$A3A EA#3AD|DЍ*ƇGSAA3AEщ$A#A3AAA3 A#A3‹kAF0Dk Ds(EFs0EؘiD{4A3‹{8#A3DS$DT$D3A DA#3ADE\AA3EA#3ADDDЍ[S,AA3T$A EA#A3AAA3A#DA3A"kDA3A DE3A#A3AAD#3D3AqEEA DA#A3Nj["DHH0"LH#"PD;Et4D;A@AzD;t AAu8D@#8H!DH!DH!D3DCXAAiA3f(DCXAAiA3f*ADCXAiA3f,DCXAAiA3f.ADCXAiA3f0DCXAAiAf2H ?"ˆ4"ˆ5""ˆ763 DH < AH H [LI[Ik VWAVH IcICLr 3HHIC9zHKHHT$PDCH = HD$HHSPHH HLHT$HL#HHL HH#IL HIHH#HL HHI%H HH%H ȸHH#H HL M;{>C #K HN  $3H\$@Hl$XH A^_^ËH HHXHhHpHx AVH D‹HP(A3DD$`EwHHu3Nt-$HHuH RMD3HhHD$XHtHM3HgHH\$0Hl$8Ht$@H|$HH A^H\$Hl$Ht$ WAVAWHpHH3HD$`H&"HH=4"3DHcH wH+HC A@Ls0DD$0HK8HD$(Lt$ EHHC(HuH 8sIUHD$(LD$@T$ EϋH'!HD$@D$0'LD$@D$(A HHD$ [_yH 댋L$Hыcc cccHHC(HCP  щS3HL$`H3L\$pI[(Ik0Is8IA_A^_H\$Hl$Ht$ WAVAWHHH3HD$pH HH= 3DHcH wH+HC A@Ls0DD$0HK8HD$(Lt$ EHaHC(HuH IUHD$(LD$@T$ EϋH'F HD$@D$0'LD$@D$(A0HHD$ ]yH 댋L$Hыcc cccHHC(HCP  щS3HL$pH3sL$I[(Ik0Is8IA_A^_H\$Hl$Ht$ WAVAWHpHH3HD$`H6HH=D3DHcH wH+HC A@Ls0DD$0HK8HD$(Lt$ EHHC(HuH (IUHD$(LD$@T$ EϋH'HD$@D$0'LD$@D$(A HHD$ k\yH 댋L$Hыcc cccHHC(HCP  щS3HL$`H3L\$pI[(Ik0Is8IA_A^_Hl$Ht$WATAUAVAWHHH3H$HHL$(3H$0E3L-HcH DD$pT$qwMVDHF !l$0HN(H!l$(DF@E3ɉVDHD$ VHFHJHDGHG(AHD$xAHO0DGHT$xF@HG HuH ]OOHGHHu H 9ov;E3+HOHIHGHI<t I;orH MH oMuE3AEw FHAONXHu3HG(AL{MĉL$h$8Dt$`L$X$ L$PL$pL$HL$qL$@H$Hd$8d$0HD$(l$ & H$D$0'@l$(L$HL$ IDM?YyH P[HF$fNDHF F$ff@n fVfFHtN$I̓g H׉G tH 녋W H FVDH E3H$H3L$Ik8Is@IA_A^A]A\_HHHE3LHcH w MEAIIHD$8D$0D$(LL$ A-yH 83HHH\$Ht$H|$AVH ADALH9HHHHuH 3-H3DGHGu_HOIHH EHH\$0Ht$8H|$@H A^H\$Ht$H|$AVH AHqLHpHHHuH 93,HFL3HG^HOIHH HH\$0Ht$8H|$@H A^H\$H|$UH$HPHoH3H@Hd$HHD$@HD$(HHHED$0 DvEAD$@DAAA D$D@A ȋ E AD AAD HDL$PH Hd$ f#fL$TAAff fAfAffA fAfA ȉD$ZCfT$XHT$ fL$VHfD$^g.H@H3L$PI[I{ I]HXH*H3H$@D HD$@AE HD$(E3AE# D$0AL\$ A A AE#A ɉT$D D$@L\$HL$PHT$ H ]D\$TCH$@H3HXH8DL$XH LL$XLL$ HVEDHH HDH8H(HE3LHcP wLHH}HH} $IPHIAHИH HDH( HHXHpHx UATAUAVAWHhHpHH3H`HE3LDL$$DD$(AfT$ HcH w IAHDcAHfL$"wEI #[HLHD$`EvAAH  HD$HA L|$hƃtRHEHD$0HEHD$8tD$P@LuD$`0L}@A0D$P8D$`(E~$A0D$` Dt$PALt$0E~L|$8DT$$@AE щT$dAA%A  A%AA  D$ ffD$tD$"ffD$vL$pAD$xA@D$|HAP DDD$(AEL AII%MIAL I$IM L M#I %?M#L IAHH H#L AIH#L ȋIL HL IIM IM LMt`t HAHHI#йH#@H HHH%I#H HH H ׁIAkHAHHI#йH#@H HHH%I#H HD$0HH H HHD$8ˉPω]}Hd$@HT$@I:)H`H3L$pI[8Is@I{HIA_A^A]A\]@UH$HPHH3H@HE3LLc@ Aw N rHD$@hAHD$(A# D$@ D$H@T$DAB%D$PD$LAvD$XA# D$`L$d A# D$hA# D$p  ЉT$lD$xA# A# D$| EAȉT$t3DD$TDD$\EEE?fdJDIHH |Hd$ HT$ ID$0P=H@H3HP]HHXHpHx UHHPH?H3H@HH3HcH w H3HL$@3HD$ AHD$0$VHD$@A*HD$(HDD$0xt @fD$43HL$@UHfHfVD$@ZfD$DCTD$FCXfD$JD$LD$Pft$TCTD$VCXfD$ZD$\VD$`ZfD$dHT$ D$f JH@H3L$PI[Is I{(I]@SHPHH3H$@HHD$@HD$(DHT$ LD$0E2D$@ DyAC@AADA HHD AD %A D  %D D A@D8 DD$DtAA=~ tA;vAAAA HHˉD$LA+ƒHT$ DEADL$HR;H$@H3~HP[HHXHpHxL` UAVAWHHPHH3H@DRHD$@Hd$ HHd$HDH5?IHD$(E#AE#IAM#ǁfAI D$0(A D$@T$DAHA AI#E#AA A ȃL$PHvI#ffD$THHH fD\$VHHI#IH HI#HH HHH HHHI#I#H HHL HH IHHI#H L HT$XIHHI#I#L HHIHH HHI#H I#HH HL HT$ LD$``9H@H3L$PI[ Is(I{0Mc8IA_A^]H\$WH H= *H1Hx%H\$0H _H\$Hl$Ht$WATAUAVAWH H1 3DLDDL`BT8lZLtu:A8Mu1Ax u*Mp$3HLȍAʼnEMII5t@8= Au`h3huLxlL`H`L`BTl:uE/h3huHxD0lH` H`tE)r+ H  <$)nmt шnHt ։ <$EtA@NjH\$PHl$XHt$`H A_A^A]A\_@SH HT$8H@T$8t DHK ƒ<t$B33IuH [H\$Hl$Ht$WAVAWH0H 3H  9xthH GH H D^]%D!=z H!=i !=g AE3EHAW"3AAHHM+uENfl$ EHAV@3utuAfAH ~H lH33HH P?=t腩tH !Abb'W33螫B3*38AEǀ=t3D0:33H\$PHl$XHt$`H0A_A^_@UH$HPH(H3H@HLDH AHd$HHD$@Hd$ HD$(A% D$0(A%AA D$@ D$D@AL$PAAA D$TAf#IfD$XfD$`D$ZBfD$^D$bBHT$ fD$fYH@H3HP]H8HH HcP 3w HD@AD$(D$ >yH B3H8A3DEA;vdAA#Ƀ w*tA+t=A+ttt u61,'@t@ttu A ED;rÅu3Ëы%EEAAuADA@AʁDEʅAAAED@DEAEɅA@AHH(tH +XH $tm H^  $uu]u8uH(@SH0DBHDJEDR AA%AD A%AA ALBD H#~AD\$(% A%AA E AA‰L$ %HD A%AA AD VH0[øuEu<@u3 u*u!uuuDAAуDA$ADDAȃ$AADȋу$ADыʃ$ADʋу@$ ADы$@ADʋ$ADѹf#fADʺ f#‹fADѹf#fADʺf#‹fADѹf#fADʺf#‹fADѹ@f#fDʋfEIDɋуDfA$fDDAf$AfADf$AfDDfA$AfDDAf $@AfADAf@%AfDfA A@%AfDfA A%AfDfA A%AfDfA A %AfDfA A%AfDfA A% AfDfA A%@AfDfA %fDѹf AfD@SH03D HH DD$(HD$ EZH %f; BtÁ~H k2*H0[HHXHhHpHx AVH HE33t@uaHc@uP@uȎÁ NY2tO-tJAA:uH FAHtEH\$0@Ht$@Hl$8H|$HH A^ÃdtuH\$Ht$H|$H\$Ht$AH|$fA>3AA ESAAfDAAAA A" A&A*A.#-A2<PA6dA:,fDR"HB HBfBBBBB(B$B4B0B,B8B<@SH a DʃaLуaAE$DADAfA A Y"ADAJ#AsAB AA2ABE3EJAZ$A AJfABAJ fABAJfABfABH [H\$WH Asivbы fHHtL3HCHH\$0H _H(Ht sivbH(H8H5E3H CHcP w LAI<EAI2D$('D$ "yH s}3H8H\$ UVWATAUAVAWHPHH3H$@I;PPLT$@EHLFHL$0HHT$ ILD$(AAÁAA# MAAAA#I  AAOыA# ЋA#  ARIWLHI#IL HIHI#L HH#IL HH#IHHH HHI#H HHH#H HL MBAMrAAA۽HHHEO @CLO@ы% ЋA#  ACL0ы% ЋA#  AVKTALHI#IL HIH#HI#L HH#IL HHH IHHH#H HH#HH HL MFKT(LHII#L HIHI#L HH#IL HIH#HIH AHHH#I#H AHH HL MFIHH|$ Ht$(Hl$0 IEAL@CLAfA# ЋA#  AKTLHI#IL HIHI#IL HH#IL HH#IHHH HHI#H I#HH HL MFHVPH;v0++HT$@DH͋@HN(HT$@HD{@H~(@tH'H$@H3H$HPA_A^A]A\_^]H\$Ht$H|$AVH M3HIADB ?Af ADAAAFAOD ЋD ȋƃE ANO A#ы L$P   AVс Ћ8A# H HD$XAVLL#HHHL HH#IL HIHH#HL HII#H\$0Ht$8H|$@HH HHH ѹHH#H HL MFH A^H\$Ht$H|$AVH M3HIADB0=ADAAFAOAD D EG AN O A#ы L$P   AVс Ћ0A# H HD$XAVLL#HHHL HH#IL HIHH#HL I#HIHH HH\$0HHt$8H|$@H HH#H HL MFH A^H\$Ht$H|$AVH M3HIADB <ADAAFA!OAD D EO A#ы L$P   AVс Ћ8A# H HD$XAVLL#HHHL HH#IL HIHH#HL I#HIHH HȁHH ѹHH#H\$0H Ht$8H|$@HL MFH A^H\$Hl$Ht$WAVAWH M3ILDB@:$H q$DDAAFAOAD AD ˅EAOIA E A#ҋ    AvE@t DtDMAAWfE+ffE+fA ff fHf#Hf Ѹ@fD HfAAfA fAVEDffAFHU LHHL#L HHHH#IL HH#IL HI#IH HHH#I#H HH ʋT$`HL MF$A0ɃAˋ$D AF $%PHD$hfAFffAN$LfAV&L#HHHI#L HH#IL HH#IL HHH IHHI#H#H HH HL MF(H\$@Hl$HHt$PH A_A^_Hl$VWATAVAWH H3!|$`3!|$hDLc@ Aw JHtǀ@~@ <$H_D~D$`HNǀ@~A <$H9D~L$`D$hL$`D|L$`lL$` D[D$hDDExH9xt AAExHA΋P HH ExAȸHH x0FD%A HADL M II Hl$PHH A_A^A\_^HXH-H >HcP 3w HD@A.D$@D$8D$0D$(d$ )yH |pw3HX@SH@HE3HE3d$8H ƃm HƃoH`ǃ@ǃ0HD$0HT$(3ǃǃƃD$ AtH nѼH n軼tH0t H nH n艼tHx0lt H nH nWtH0t H nX3H@[HHBLуHjypUC A  H? $Hd$0E3D$(AD$ IX,uH HL$pHHHHBLуHE3ۅyACpHL$pD $UC A  HD $L\$0E3D$(AD$ I+HHH\$Hl$Ht$WAVAWH 3LH3 ALH /3uPDH0u/D8 u#Kzx@3xHH؀xE uD8 u {xuH;u%HH4A+v u$ oHH H4HA+ vnu3JwdH wTHHHA+Jv6Jw1HDD;s HHcHAHA+JvօIDMtIH\$@HHt$PHl$HH A_A^_H\$Hl$ VWAVHHH3H$AADHEy$ہ3HL$@DB@1D$0'_D$(LD$@A@ Aց  $L$@@D$Df f$fff f f fL$HH$D$JAHfD$NHD$@HD$ )ȅuD$H ȸ;sH$H3aL$I[ Ik8IA^_^@USVWATAVAWHl$HHH3HEHuwDLu3ALHMADB@0MgӁ@E @}ǁ%O ЋO %  f f ]offfEUCEMu fED$0'HED$(LEA@HD$ AIQ(HtYEEfFt9t&tu8EFEfFEىFEfFEщF EfFEɉFEfF MtEϋ AM HMH3譵HĐA_A^A\_^[]H\$Hl$Ht$ WATAUAVAWH HBHxDjHHHD$PIuH} ?+CDs E3AHH{(thA@AE;HEBHT$PE/E+t% AF3DuH{(H@AD;rAHǨtH AF3DC 3HC ,sKDs H Ή $3H\$XHl$`Ht$hH A_A^A]A\_HhHH3HD$P3D$0'HD$@LHD$HDAAAD$(Hd$ o AA%AA LD$@ $ ȉT$@$A L$DI%HL$PH3蜳HhH\$Hl$Ht$ WAVAWH HEًADmDDP ;B؋SHhADA A A A A A A ʉ  $A@$A:AE:ARHYt'PHLD$HlL$H;G؃w3_ uC x@H H ;% ‰ $HoHb$HU $ $H8$JH)DAIHAD;% A ȉ $HHDD $HLSH#ʉL $HPH#ʉP $H}AOx $H\$@3Hl$PHt$XH A_A^_H\$UVWHHzH3H$A3HHL$@ADB@*DD$0'AD$(D$D@A@D A%oAD HAo % D $fD fD$HHD$@DD$@LD$@HD$ g"H$H3OH$HĐ_^]@SUVWATAVAWH`HH3HD$PH$LAؾDE3AA ADN D AAAD AA D E A3D$0'HD$@LD$@HD$HAHD$@D$(AHD$ ID$@D$DDt$Hv!؅t4tu΅Ho0I=D$Hȁ Hty utA;to0uPpH20uً΅2Hty sus HL$PH3rH`A_A^A\_^][LHhHH3HD$P3D$0'ICMCICD$(I!CDHD$@D$D HL$PH3HhLHhHRH3HD$P3D$0'ICICAD$@DHD$DECMCD$(I!CHL$PH3螭HhH(HE3D<AtRtAt0t=t,tDH]A+t0 t"A;H9sLfH ZV@H qV7AJEB H U?贡H xU裡zH gVH >Vǃ@t\tWidtH PV[2A8Z("3H9LII~BWwAJAABDDA%AD AA#AD A# AAJA?DD AA#D A# AH hTD EƋDd$ A# Eρ N8u"D5-D=D%D-;AD݋H\$`Hl$hHt$pH0A_A^A]A\_@SUVWATAUAVAWH8HBLDjHID$LHD$ I~tA+s"H cS螟H8A_A^A]A\_^][I$HAnw̃?HE3H@D$A@AE;HEBHT$ ED$E+D$t'AG3u H@H@AD;rAHƨtH AG3$3H8D46$ɍIqAF$hH$3HHH@$twA@HE;EBHT$ EE+t6G3A7u H@H@$$;$rA@s D$ G3A7$MMHHȋ$H@H $3A7H8D43ҋ$A7$0H ͉ $3HHXHhVWAVH03L@DfXHXX S{0D$ tZLD$`H͍S4aD$`<@r@$LD$hH͋ֈD$`?D$hD$ADAMIʋ#A# D AD DHvIuAH$H3跕HĐA_A^A]A\_^]E3MHAɁ} $H}A?fA#fMt A AHIA|HAPE3D@AEAAE ЉAA;tv D D+EED+D)IDQA@SH HHً0y(DHHgIH BAHNa#H [H\$UVWAVAWHHfH3H$$Lt$HAADHv 3HL$@DB@ D$D ȋ%_ ȋ_ %  ΉL$@tzL$AL$M+C ыA# Ћ A DM[ AA%MvD A# AD EFu$LD$@D$0A@D$(AHd$ HhH$H3PH$HĐA_A^_^]@SVWH`HeH3HD$P$HED$0'AȺAIAAAI؋$DIЋ$DI؋$DI3HD$@_HD$HA D$DAAA  ȋ‰L$@  A A A A A A %AA A?A AA $ ˈD$(Hd$ L$HLD$@HHL$PH3֑H`_^[H\$UVWATAUAVAWH HHE3LHAHcP w HIFHHD$hEI_M9fuM9&t^EFArTA`w&MH'AIEy+NAA;sKH E#Iʍ RDJDA@vH OEʑH\$pH A_A^A]A\_^]ËF APDЉD$`EADILV(ʋ% MbA#  AA A ABAFftHH,H DAUAE# fEb Mb A ARAFANff HH fAJHHH#HHH HHH#H AHIJII,EtrLnPHT$hI;vCAA+DNj8 EFHT$hD+HN(H AF++A+HHN(D/EF AN+A+DI3MLHD$`3A6HF D43ҋF D~A6NV H6A ω $3@SH HHًtu( PHDAt At3H=HBH [H\$Hl$Ht$AVH HAADA AȸA;t3\$PtN|$Xt L$XMPHVA ͸;uHD$`Ht3H\$0Hl$8Ht$@H A^øH\$UVWATAUAVAWHH:`H3H$H$PEH$LDL$h IHL$xT$`ML$D@DL$dAA@$`DDL|$pD3D+3H nAڃu|tI3H^DPEH,AQ8 HlAQ0HH H HtAQ(HH H H޼|AQ HϼH H H\AQHH Hً HD\AQHI Lً H}DTAQHmI Lы H\DDHPI LA H>ELH9Hl$PHt$Ht$`H|$@H\$8L\$0I LT$(LLD$ ID}L$IE3ɻED\$dHIIILHHL#L HHHI#IL HI#IL H%IH HH%H H#H^HH HL C D $H<I DD $AMRE;cL|$pLl$xt$`HA $HA3H0A;LHA t!$<uuHA $HAƙDrDl$dL$IH QA4H DDDH8H.DLH"HDTH HD\H,HDHH׹DH̹H¹DH HDAI AH LIII#HL IIAH I#L AH I#IL %IH ȺH%H ȋHH#H HL MMvADt$hL|$pLl$x IHA $H$HH%HH IHH%H HH#HH HHHI#HI#I#H $HH HH H HH8.text$s.idata$5.00cfg0.gfidsH.rdata.rdata$zzzdbg.xdata ].data}.bss$.pdataPAGEFW0\INIT\0<.idata$20.idata$30.idata$4@1^.idata$6@`.rsrc$01`@.rsrc$02 t!4  P20 dT4rp  4 pB2 p ` 0b! 4njp`P0N@ np`P00N`d42 p&4jhP0N0 dT4p t d T 4R  td42 p`P00N tdT4t d T 42  4 2p *00N@ d T 42p$ p`P00Nh 42 .p0N`* 48. p`P0N`2 tO dN TM 4L H0N0 dT42pi0N0 dT42p &p`P00N  t d T 42 b p`P0 d T 4 Rp J00N@ t dT42K0N@1 #t,#d+#4*#$P0N)&00N  4* (p0N0 T 4 R p `) 4& p`P0N  p`P00N`d 4 r p'  p`0P0N# 4 p`P0NHW0d 4R p T 4 2 p ` t dT42  p`P00NP0NP d T 42p%  p`P0N% 4 p`P0N%  p`0P0N! 4p`P0Np`00NP' T4 p `0N0NP  dT42R0t d4 td42 T 42 p `, d"T! p0N' dT4p0N`* dT4p0Npr0) 4UJ p`P0N@ 42 p`P N&b p`P0 d T 4 2p dT 4 Rp d T 4 2p/ tOdN4MJP0N@ T 2 p`7 &tW&dV&4U&NP0N`7&Q&tP&dO&4N&JP0N@"JP0N@+ tN4MJ P0N@bB) 4  p`P0NABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789+/=2-+] f@@@@0@P@p@@<<00000Y Y$Y`Y`YhYhYpYpYxYxYYYYYYYYYYYZZZZZZZZ``aPabb@bHbbbb8cpccd>@,@A|@LZ(\ &(D 4 ` !!!!###4#$$O%hP%&&(h(++V,X,,\,0011Y2P\233@$@IALABBBB D DBDDDaLdLMMN0NMN4PNN4NVhVWW8X8XXXZZ[[]]^\___ a abbdd3gt4gg@g8hD8hhDhjhjjTj-k0kkkNoPopPp@r@r{s |su$uuuwwx xzz{P{|{\l||4|}$h$80``40\0>@D8D8DUXƐȐGH,@,Γ@ГJLUxX\Y\WX444`@ͫЫ4\4|i@ldFHh,hL0<<T"$$]` Op7PUi*0+0# Chelsio T6 SMB direct configuration file. # # Copyright (C) 2010-2017 Chelsio Communications. All rights reserved. # # DO NOT MODIFY THIS FILE UNDER ANY CIRCUMSTANCES. MODIFICATION OF THIS FILE # WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE # TO ADAPTERS. # This file provides the default, power-on configuration for 2-port T6-based # adapters shipped from the factory. These defaults are designed to address # the needs of the vast majority of Terminator customers. The basic idea is to # have a default configuration which allows a customer to plug a Terminator # adapter in and have it work regardless of OS, driver or application except in # the most unusual and/or demanding customer applications. # # Many of the Terminator resources which are described by this configuration # are finite. This requires balancing the configuration/operation needs of # device drivers across OSes and a large number of customer application. # # Some of the more important resources to allocate and their constaints are: # 1. Virtual Interfaces: 256. # 2. Ingress Queues with Free Lists: 1024. # 3. Egress Queues: 128K. # 4. MSI-X Vectors: 1088. # 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination # address matching on Ingress Packets. # # Some of the important OS/Driver resource needs are: # 6. Some OS Drivers will manage all resources through a single Physical # Function (currently PF4 but it could be any Physical Function). # 7. Some OS Drivers will manage different ports and functions (NIC, # storage, etc.) on different Physical Functions. For example, NIC # functions for ports 0-1 on PF0-3, FCoE on PF4, iSCSI on PF5, etc. # # Some of the customer application needs which need to be accommodated: # 8. Some customers will want to support large CPU count systems with # good scaling. Thus, we'll need to accommodate a number of # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs # to be involved per port and per application function. For example, # in the case where all ports and application functions will be # managed via a single Unified PF and we want to accommodate scaling up # to 8 CPUs, we would want: # # 4 ports * # 3 application functions (NIC, FCoE, iSCSI) per port * # 16 Ingress Queue/MSI-X Vectors per application function # # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF. # (Plus a few for Firmware Event Queues, etc.) # # 9. Some customers will want to use PCI-E SR-IOV Capability to allow Virtual # Machines to directly access T6 functionality via SR-IOV Virtual Functions # and "PCI Device Passthrough" -- this is especially true for the NIC # application functionality. # # Global configuration settings. # [global] rss_glb_config_mode = basicvirtual rss_glb_config_options = tnlmapen,hashtoeplitz,tnlalllkp rss_keymode = idxvf_key #Other modes: glb_key, glbvf_key, pfvf_key # PL_TIMEOUT register pl_timeout_value = 200 # the timeout value in units of us # The following Scatter Gather Engine (SGE) settings assume a 4KB Host # Page Size and a 64B L1 Cache Line Size. It programs the # EgrStatusPageSize and IngPadBoundary to 64B and the PktShift to 2. # If a Master PF Driver finds itself on a machine with different # parameters, then the Master PF Driver is responsible for initializing # these parameters to appropriate values. # # Notes: # 1. The Free List Buffer Sizes below are raw and the firmware will # round them up to the Ingress Padding Boundary. # 2. The SGE Timer Values below are expressed below in microseconds. # The firmware will convert these values to Core Clock Ticks when # it processes the configuration parameters. # reg[0x1008] = 0x40800/0x21c70 # SGE_CONTROL reg[0x100c] = 0x22222222 # SGE_HOST_PAGE_SIZE reg[0x10a0] = 0x01040810 # SGE_INGRESS_RX_THRESHOLD reg[0x1044] = 4096 # SGE_FL_BUFFER_SIZE0 reg[0x1048] = 65536 # SGE_FL_BUFFER_SIZE1 reg[0x104c] = 1536 # SGE_FL_BUFFER_SIZE2 reg[0x1050] = 9024 # SGE_FL_BUFFER_SIZE3 reg[0x1054] = 9216 # SGE_FL_BUFFER_SIZE4 reg[0x1058] = 2048 # SGE_FL_BUFFER_SIZE5 reg[0x105c] = 128 # SGE_FL_BUFFER_SIZE6 reg[0x1060] = 8192 # SGE_FL_BUFFER_SIZE7 reg[0x1064] = 16384 # SGE_FL_BUFFER_SIZE8 sge_timer_value = 5, 10, 20, 50, 100, 200 # SGE_TIMER_VALUE* in usecs reg[0x10c4] = 0x20000000/0x20000000 # GK_CONTROL, enable 5th thread # enable TP_OUT_CONFIG.IPIDSPLITMODE reg[0x7d04] = 0x00010000/0x00010000 # TP_SHIFT_CNT - set SYN shift count to 4 for quicker connect timeouts reg[0x7dc0] = 0x042f8849 # TP_SHIFT_CNT #Tick granularities in kbps tsch_ticks = 100000, 10000, 1000, 10 # TP_VLAN_PRI_MAP to select filter tuples and enable ServerSram # filter control: compact, fcoemask # server sram : srvrsram # filter tuples : fragmentation, mpshittype, macmatch, ethertype, # protocol, tos, vlan, vnic_id, port, fcoe # valid filterModes are described the Terminator 5 Data Book filterMode = fcoemask, fragmentation, mpshittype, macmatch, protocol, tos, port, fcoe # filter tuples enforced in LE active region (equal to or subset of filterMode) filterMask = protocol, fcoe # Percentage of dynamic memory (in either the EDRAM or external MEM) # to use for TP RX payload tp_pmrx = 20 # TP RX payload page size tp_pmrx_pagesize = 64K # TP number of RX channels tp_nrxch = 0 # 0 (auto) = 1 # Percentage of dynamic memory (in either the EDRAM or external MEM) # to use for TP TX payload tp_pmtx = 30 # TP TX payload page size tp_pmtx_pagesize = 64K # TP number of TX channels tp_ntxch = 0 # 0 (auto) = equal number of ports # TP OFLD MTUs tp_mtus = 88, 256, 512, 576, 808, 1024, 1280, 1488, 1500, 2002, 2048, 4096, 4352, 8192, 9000, 9600 # enable TP_OUT_CONFIG.IPIDSPLITMODE and CRXPKTENC reg[0x7d04] = 0x00010008/0x00010008 # TP TCP hardware stack tuning tp_tcptuning = cluster # wan, lan or cluster # TP_GLOBAL_CONFIG reg[0x7d08] = 0x00000800/0x00000800 # set IssFromCplEnable # TP_PC_CONFIG reg[0x7d48] = 0x00000000/0x00000400 # clear EnableFLMError # TP_PARA_REG0 reg[0x7d60] = 0x06000000/0x07000000 # set InitCWND to 6 # LE_DB_CONFIG reg[0x19c04] = 0x00000000/0x00440000 # LE Server SRAM disabled # LE IPv4 compression disabled # LE_DB_HASH_CONFIG reg[0x19c28] = 0x00800000/0x01f00000 # LE Hash bucket size 8 # ULP_TX_CONFIG reg[0x8dc0] = 0x00000004/0x00000004 # Enable more error msg for ... # TPT error. # ULP_RX_MISC_FEATURE_ENABLE #reg[0x1925c] = 0x01003400/0x01003400 # iscsi tag pi bit # Enable offset decrement after ... # PI extraction and before DDP # ulp insert pi source info in DIF # iscsi_eff_offset_en #Enable iscsi completion moderation feature reg[0x1925c] = 0x000041c0/0x000031c0 # Enable offset decrement after # PI extraction and before DDP. # ulp insert pi source info in # DIF. # Enable iscsi hdr cmd mode. # iscsi force cmd mode. # Enable iscsi cmp mode. # HMA configuration hma_size = 96 # Size (in MBs) of host memory expected hma_regions = stag,pbl,rq # What all regions to place in host memory # Some "definitions" to make the rest of this a bit more readable. We support # 4 ports, 3 functions (NIC, FCoE and iSCSI), scaling up to 8 "CPU Queue Sets" # per function per port ... # # NMSIX = 1088 # available MSI-X Vectors # NVI = 256 # available Virtual Interfaces # NMPSTCAM = 336 # MPS TCAM entries # # NPORTS = 2 # ports # NCPUS = 16 # CPUs we want to support scalably # NFUNCS = 3 # functions per port (NIC, FCoE, iSCSI) # RSSNSECRET = 16 # available 320b entries in rss secret table # Breakdown of Virtual Interface/Queue/Interrupt resources for the "Unified # PF" which many OS Drivers will use to manage most or all functions. # # Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can # use Forwarded Interrupt Ingress Queues. For these latter, an Ingress Queue # would be created and the Queue ID of a Forwarded Interrupt Ingress Queue # will be specified as the "Ingress Queue Asynchronous Destination Index." # Thus, the number of MSI-X Vectors assigned to the Unified PF will be less # than or equal to the number of Ingress Queues ... # # NVI_NIC = 4 # NIC access to NPORTS # NFLIQ_NIC = 32 # NIC Ingress Queues with Free Lists # NETHCTRL_NIC = 32 # NIC Ethernet Control/TX Queues # NEQ_NIC = 64 # NIC Egress Queues (FL, ETHCTRL/TX) # NMPSTCAM_NIC = 16 # NIC MPS TCAM Entries (NPORTS*4) # NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ) # # NVI_OFLD = 0 # Offload uses NIC function to access ports # NFLIQ_OFLD = 16 # Offload Ingress Queues with Free Lists # NETHCTRL_OFLD = 0 # Offload Ethernet Control/TX Queues # NEQ_OFLD = 16 # Offload Egress Queues (FL) # NMPSTCAM_OFLD = 0 # Offload MPS TCAM Entries (uses NIC's) # NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ) # # NVI_RDMA = 0 # RDMA uses NIC function to access ports # NFLIQ_RDMA = 4 # RDMA Ingress Queues with Free Lists # NETHCTRL_RDMA = 0 # RDMA Ethernet Control/TX Queues # NEQ_RDMA = 4 # RDMA Egress Queues (FL) # NMPSTCAM_RDMA = 0 # RDMA MPS TCAM Entries (uses NIC's) # NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ) # # NEQ_WD = 128 # Wire Direct TX Queues and FLs # NETHCTRL_WD = 64 # Wire Direct TX Queues # NFLIQ_WD = 64 ` # Wire Direct Ingress Queues with Free Lists # # NVI_ISCSI = 4 # ISCSI access to NPORTS # NFLIQ_ISCSI = 4 # ISCSI Ingress Queues with Free Lists # NETHCTRL_ISCSI = 0 # ISCSI Ethernet Control/TX Queues # NEQ_ISCSI = 4 # ISCSI Egress Queues (FL) # NMPSTCAM_ISCSI = 4 # ISCSI MPS TCAM Entries (NPORTS) # NMSIX_ISCSI = 4 # ISCSI MSI-X Interrupt Vectors (FLIQ) # # NVI_FCOE = 4 # FCOE access to NPORTS # NFLIQ_FCOE = 34 # FCOE Ingress Queues with Free Lists # NETHCTRL_FCOE = 32 # FCOE Ethernet Control/TX Queues # NEQ_FCOE = 66 # FCOE Egress Queues (FL) # NMPSTCAM_FCOE = 32 # FCOE MPS TCAM Entries (NPORTS) # NMSIX_FCOE = 34 # FCOE MSI-X Interrupt Vectors (FLIQ) # Two extra Ingress Queues per function for Firmware Events and Forwarded # Interrupts, and two extra interrupts per function for Firmware Events (or a # Forwarded Interrupt Queue) and General Interrupts per function. # # NFLIQ_EXTRA = 6 # "extra" Ingress Queues 2*NFUNCS (Firmware and # # Forwarded Interrupts # NMSIX_EXTRA = 6 # extra interrupts 2*NFUNCS (Firmware and # # General Interrupts # Microsoft HyperV resources. The HyperV Virtual Ingress Queues will have # their interrupts forwarded to another set of Forwarded Interrupt Queues. # # NVI_HYPERV = 16 # VMs we want to support # NVIIQ_HYPERV = 2 # Virtual Ingress Queues with Free Lists per VM # NFLIQ_HYPERV = 40 # VIQs + NCPUS Forwarded Interrupt Queues # NEQ_HYPERV = 32 # VIQs Free Lists # NMPSTCAM_HYPERV = 16 # MPS TCAM Entries (NVI_HYPERV) # NMSIX_HYPERV = 8 # NCPUS Forwarded Interrupt Queues # Adding all of the above Unified PF resource needs together: (NIC + OFLD + # RDMA + ISCSI + FCOE + EXTRA + HYPERV) # # NVI_UNIFIED = 28 # NFLIQ_UNIFIED = 106 # NETHCTRL_UNIFIED = 32 # NEQ_UNIFIED = 124 # NMPSTCAM_UNIFIED = 40 # # The sum of all the MSI-X resources above is 74 MSI-X Vectors but we'll round # that up to 128 to make sure the Unified PF doesn't run out of resources. # # NMSIX_UNIFIED = 128 # # The Storage PFs could need up to NPORTS*NCPUS + NMSIX_EXTRA MSI-X Vectors # which is 34 but they're probably safe with 32. # # NMSIX_STORAGE = 32 # Note: The UnifiedPF is PF4 which doesn't have any Virtual Functions # associated with it. Thus, the MSI-X Vector allocations we give to the # UnifiedPF aren't inherited by any Virtual Functions. As a result we can # provision many more Virtual Functions than we can if the UnifiedPF were # one of PF0-3. # # All of the below PCI-E parameters are actually stored in various *_init.txt # files. We include them below essentially as comments. # # For PF0-3 we assign 8 vectors each for NIC Ingress Queues of the associated # ports 0-3. # # For PF4, the Unified PF, we give it an MSI-X Table Size as outlined above. # # For PF5-6 we assign enough MSI-X Vectors to support FCoE and iSCSI # storage applications across all four possible ports. # # Additionally, since the UnifiedPF isn't one of the per-port Physical # Functions, we give the UnifiedPF and the PF0-3 Physical Functions # different PCI Device IDs which will allow Unified and Per-Port Drivers # to directly select the type of Physical Function to which they wish to be # attached. # # Note that the actual values used for the PCI-E Intelectual Property will be # 1 less than those below since that's the way it "counts" things. For # readability, we use the number we actually mean ... # # PF0_INT = 8 # NCPUS # PF1_INT = 8 # NCPUS # PF2_INT = 8 # NCPUS # PF3_INT = 8 # NCPUS # PF0_3_INT = 32 # PF0_INT + PF1_INT + PF2_INT + PF3_INT # # PF4_INT = 128 # NMSIX_UNIFIED # PF5_INT = 32 # NMSIX_STORAGE # PF6_INT = 32 # NMSIX_STORAGE # PF7_INT = 0 # Nothing Assigned # PF4_7_INT = 192 # PF4_INT + PF5_INT + PF6_INT + PF7_INT # # PF0_7_INT = 224 # PF0_3_INT + PF4_7_INT # # With the above we can get 17 VFs/PF0-3 (limited by 336 MPS TCAM entries) # but we'll lower that to 16 to make our total 64 and a nice power of 2 ... # # NVF = 16 # Some OS Drivers manage all application functions for all ports via PF4. # Thus we need to provide a large number of resources here. For Egress # Queues we need to account for both TX Queues as well as Free List Queues # (because the host is responsible for producing Free List Buffers for the # hardware to consume). # [function "4"] wx_caps = all # write/execute permissions for all commands r_caps = all # read permissions for all commands nvi = 34 # NVI_UNIFIED rssnsecret = 16 # all 16 table entries to PF 4 rssnvi = 32 niqflint = 170 # NFLIQ_UNIFIED + NLFIQ_WD nethctrl = 100 # NETHCTRL_UNIFIED + NETHCTRL_WD neq = 256 # NEQ_UNIFIED + NEQ_WD nexactf = 256 # NMPSTCAM_UNIFIED nrawf = 2 nqpcq = 12288 cmask = all # access to all channels pmask = all # access to all four ports ... nclip = 384 # number of clip region entries nfilter = 368 # number of filter region entries nserver = 128 # number of server region entries nhash = 14336 # number of hash region entries protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu tp_l2t = 4096 tp_ddp = 1 tp_ddp_iscsi = 1 tp_stag = 5 tp_pbl = 34 tp_rq = 10 [function "6"] wx_caps = all # write/execute permissions for all commands r_caps = all # read permissions for all commands nvi = 4 # NPORTS niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA nethctrl = 32 # NPORTS*NCPUS neq = 66 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) + 2 (EXTRA) nexactf = 32 # NPORTS + adding 28 exact entries for FCoE # which is OK since < MIN(SUM PF0..3, PF4) # and we never load PF0..3 and PF4 concurrently cmask = all # access to all channels pmask = all # access to all four ports ... nhash = 2048 tp_l2t = 4 protocol = fcoe_initiator tp_ddp = 2 fcoe_nfcf = 16 fcoe_nvnp = 32 fcoe_nssn = 1024 # The following function, 1023, is not an actual PCIE function but is used to # configure and reserve firmware internal resources that come from the global # resource pool. # [function "1023"] wx_caps = all # write/execute permissions for all commands r_caps = all # read permissions for all commands nvi = 4 # NVI_UNIFIED cmask = all # access to all channels pmask = all # access to all four ports ... nexactf = 8 # NPORTS + DCBX + nfilter = 16 # number of filter region entries # For Virtual functions, we only allow NIC functionality and we only allow # access to one port (1 << PF). Note that because of limitations in the # Scatter Gather Engine (SGE) hardware which checks writes to VF KDOORBELL # and GTS registers, the number of Ingress and Egress Queues must be a power # of 2. # [function "0/*"] # NVF nvi = 1 # 1 port rssnvi = 0 [function "1/*"] # NVF nvi = 1 # 1 port rssnvi = 0 [function "2/*"] # NVF nvi = 1 # 1 port rssnvi = 0 [function "3/*"] # NVF nvi = 1 # 1 port rssnvi = 0 [function "4/*"] # NVF wx_caps = 0x82 # DMAQ | VF r_caps = 0x86 # DMAQ | VF | PORT nvi = 1 # 1 port rssnvi = 1 niqflint = 11 # 8 "Queue Sets" + CIQ + FWEVTQ + FWDINTRQ nethctrl = 8 # 8 "Queue Sets" neq = 16 # 8 "Queue Sets" * 2 nexactf = 4 cmask = all # access to all channels pmask = all # access to all ports nqpcq = 78 protocol = ofld, rdmac # MPS features a 196608 bytes ingress buffer that is used for ingress buffering # for packets from the wire as well as the loopback path of the L2 switch. The # folling params control how the buffer memory is distributed and the L2 flow # control settings: # # bg_mem: %-age of mem to use for port/buffer group # lpbk_mem: %-age of port/bg mem to use for loopback # hwm: high watermark; bytes available when starting to send pause # frames (in units of 0.1 MTU) # lwm: low watermark; bytes remaining when sending 'unpause' frame # (in inuits of 0.1 MTU) # dwm: minimum delta between high and low watermark (in units of 100 # Bytes) # [port "0"] dcb = ppp, dcbx # configure for DCB PPP and enable DCBX offload dcb_dcbx_protocol = auto hwm = 60 lwm = 15 dwm = 30 dcb_app_tlv[0] = 0x8906, ethertype, 3 dcb_app_tlv[1] = 0x8914, ethertype, 3 dcb_app_tlv[2] = 3260, socketnum, 5 [port "1"] dcb = ppp, dcbx dcb_dcbx_protocol = auto hwm = 60 lwm = 15 dwm = 30 dcb_app_tlv[0] = 0x8906, ethertype, 3 dcb_app_tlv[1] = 0x8914, ethertype, 3 dcb_app_tlv[2] = 3260, socketnum, 5 [fini] version = 0x08000025 checksum = 0x7632c817 # Total resources used by above allocations: # Virtual Interfaces: 104 # Ingress Queues/w Free Lists and Interrupts: 526 # Egress Queues: 702 # MPS TCAM Entries: 336 # MSI-X Vectors: 736 # Virtual Functions: 64 # Chelsio T5 SMB configuration file. # # Copyright (C) 2010-2017 Chelsio Communications. All rights reserved. # # DO NOT MODIFY THIS FILE UNDER ANY CIRCUMSTANCES. MODIFICATION OF THIS FILE # WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE # TO ADAPTERS. # This file provides the default, power-on configuration for 4-port T5-based # adapters shipped from the factory. These defaults are designed to address # the needs of the vast majority of Terminator customers. The basic idea is to # have a default configuration which allows a customer to plug a Terminator # adapter in and have it work regardless of OS, driver or application except in # the most unusual and/or demanding customer applications. # # Many of the Terminator resources which are described by this configuration # are finite. This requires balancing the configuration/operation needs of # device drivers across OSes and a large number of customer application. # # Some of the more important resources to allocate and their constaints are: # 1. Virtual Interfaces: 256. # 2. Ingress Queues with Free Lists: 1024. # 3. Egress Queues: 128K. # 4. MSI-X Vectors: 1088. # 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination # address matching on Ingress Packets. # # Some of the important OS/Driver resource needs are: # 6. Some OS Drivers will manage all resources through a single Physical # Function (currently PF4 but it could be any Physical Function). # 7. Some OS Drivers will manage different ports and functions (NIC, # storage, etc.) on different Physical Functions. For example, NIC # functions for ports 0-3 on PF0-3, FCoE on PF4, iSCSI on PF5, etc. # # Some of the customer application needs which need to be accommodated: # 8. Some customers will want to support large CPU count systems with # good scaling. Thus, we'll need to accommodate a number of # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs # to be involved per port and per application function. For example, # in the case where all ports and application functions will be # managed via a single Unified PF and we want to accommodate scaling up # to 8 CPUs, we would want: # # 4 ports * # 3 application functions (NIC, FCoE, iSCSI) per port * # 8 Ingress Queue/MSI-X Vectors per application function # # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF. # (Plus a few for Firmware Event Queues, etc.) # # 9. Some customers will want to use PCI-E SR-IOV Capability to allow Virtual # Machines to directly access T6 functionality via SR-IOV Virtual Functions # and "PCI Device Passthrough" -- this is especially true for the NIC # application functionality. # # Global configuration settings. # [global] rss_glb_config_mode = basicvirtual rss_glb_config_options = tnlmapen,hashtoeplitz,tnlalllkp rss_keymode = idxvf_key #Other modes: glb_key, glbvf_key, pfvf_key # PL_TIMEOUT register pl_timeout_value = 10000 # the timeout value in units of us # The following Scatter Gather Engine (SGE) settings assume a 4KB Host # Page Size and a 64B L1 Cache Line Size. It programs the # EgrStatusPageSize and IngPadBoundary to 64B and the PktShift to 2. # If a Master PF Driver finds itself on a machine with different # parameters, then the Master PF Driver is responsible for initializing # these parameters to appropriate values. # # Notes: # 1. The Free List Buffer Sizes below are raw and the firmware will # round them up to the Ingress Padding Boundary. # 2. The SGE Timer Values below are expressed below in microseconds. # The firmware will convert these values to Core Clock Ticks when # it processes the configuration parameters. # reg[0x1008] = 0x40010/0x21c70 # SGE_CONTROL reg[0x100c] = 0x22222222 # SGE_HOST_PAGE_SIZE reg[0x10a0] = 0x01040810 # SGE_INGRESS_RX_THRESHOLD reg[0x1044] = 4096 # SGE_FL_BUFFER_SIZE0 reg[0x1048] = 65536 # SGE_FL_BUFFER_SIZE1 reg[0x104c] = 1536 # SGE_FL_BUFFER_SIZE2 reg[0x1050] = 9024 # SGE_FL_BUFFER_SIZE3 reg[0x1054] = 9216 # SGE_FL_BUFFER_SIZE4 reg[0x1058] = 2048 # SGE_FL_BUFFER_SIZE5 reg[0x105c] = 128 # SGE_FL_BUFFER_SIZE6 reg[0x1060] = 8192 # SGE_FL_BUFFER_SIZE7 reg[0x1064] = 16384 # SGE_FL_BUFFER_SIZE8 reg[0x10a4] = 0x00280000/0x3ffc0000 # SGE_DBFIFO_STATUS reg[0x1118] = 0x00002800/0x00003c00 # SGE_DBFIFO_STATUS2 reg[0x10a8] = 0x402000/0x402000 # SGE_DOORBELL_CONTROL # SGE_THROTTLE_CONTROL bar2throttlecount = 500 # bar2throttlecount in us sge_timer_value = 5, 10, 20, 50, 100, 200 # SGE_TIMER_VALUE* in usecs reg[0x1124] = 0x00000400/0x00000400 # SGE_CONTROL2, enable VFIFO; if # SGE_VFIFO_SIZE is not set, then # firmware will set it up in function # of number of egress queues used reg[0x1130] = 0x00d5ffeb # SGE_DBP_FETCH_THRESHOLD, fetch # threshold set to queue depth # minus 128-entries for FL and HP # queues, and 0xfff for LP which # prompts the firmware to set it up # in function of egress queues # used reg[0x113c] = 0x0002ffc0 # SGE_VFIFO_SIZE, set to 0x2ffc0 which # prompts the firmware to set it up in # function of number of egress queues # used # enable TP_OUT_CONFIG.IPIDSPLITMODE reg[0x7d04] = 0x00010000/0x00010000 # disable TP_PARA_REG3.RxFragEn reg[0x7d6c] = 0x00000000/0x00007000 # enable TP_PARA_REG6.EnableCSnd reg[0x7d78] = 0x00000400/0x00000000 # TP_SHIFT_CNT - set SYN shift count to 4 for quicker connect timeouts reg[0x7dc0] = 0x042f8849 # TP_SHIFT_CNT # TP_VLAN_PRI_MAP to select filter tuples and enable ServerSram # filter control: compact, fcoemask # server sram : srvrsram # filter tuples : fragmentation, mpshittype, macmatch, ethertype, # protocol, tos, vlan, vnic_id, port, fcoe # valid filterModes are described the Terminator 5 Data Book filterMode = fcoemask, fragmentation, mpshittype, macmatch, protocol, tos, port, fcoe # filter tuples enforced in LE active region (equal to or subset of filterMode) filterMask = protocol, fcoe # Percentage of dynamic memory (in either the EDRAM or external MEM) # to use for TP RX payload tp_pmrx = 20 # TP RX payload page size tp_pmrx_pagesize = 64K # TP number of RX channels tp_nrxch = 0 # 0 (auto) = 1 # Percentage of dynamic memory (in either the EDRAM or external MEM) # to use for TP TX payload tp_pmtx = 30 # TP TX payload page size tp_pmtx_pagesize = 64K # TP number of TX channels tp_ntxch = 0 # 0 (auto) = equal number of ports # TP OFLD MTUs tp_mtus = 88, 256, 512, 576, 808, 1024, 1280, 1488, 1500, 2002, 2048, 4096, 4352, 8192, 9000, 9600 # TP TCP hardware stack tuning tp_tcptuning = cluster # wan, lan or cluster # TP_GLOBAL_CONFIG reg[0x7d08] = 0x00000800/0x00000800 # set IssFromCplEnable # TP_PC_CONFIG reg[0x7d48] = 0x00000000/0x00000400 # clear EnableFLMError # TP_PARA_REG0 reg[0x7d60] = 0x06000000/0x07000000 # set InitCWND to 6 # ULPRX iSCSI Page Sizes reg[0x19168] = 0x04020100 # 64K, 16K, 8K and 4K # MC configuration mc_mode_brc[0] = 1 # mc0 - 1: enable BRC, 0: enable RBC mc_mode_brc[1] = 1 # mc1 - 1: enable BRC, 0: enable RBC # ULP_TX_CONFIG reg[0x8dc0] = 0x00000004/0x00000004 # Enable more error msg for ... # TPT error. # Some "definitions" to make the rest of this a bit more readable. We support # 4 ports, 3 functions (NIC, FCoE and iSCSI), scaling up to 8 "CPU Queue Sets" # per function per port ... # # NMSIX = 1088 # available MSI-X Vectors # NVI = 128 # available Virtual Interfaces # NMPSTCAM = 336 # MPS TCAM entries # # NPORTS = 4 # ports # NCPUS = 8 # CPUs we want to support scalably # NFUNCS = 3 # functions per port (NIC, FCoE, iSCSI) # RSSNSECRET = 16 # available 320b entries in rss secret table # Breakdown of Virtual Interface/Queue/Interrupt resources for the "Unified # PF" which many OS Drivers will use to manage most or all functions. # # Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can # use Forwarded Interrupt Ingress Queues. For these latter, an Ingress Queue # would be created and the Queue ID of a Forwarded Interrupt Ingress Queue # will be specified as the "Ingress Queue Asynchronous Destination Index." # Thus, the number of MSI-X Vectors assigned to the Unified PF will be less # than or equal to the number of Ingress Queues ... # # NVI_NIC = 4 # NIC access to NPORTS # NFLIQ_NIC = 32 # NIC Ingress Queues with Free Lists # NETHCTRL_NIC = 32 # NIC Ethernet Control/TX Queues # NEQ_NIC = 64 # NIC Egress Queues (FL, ETHCTRL/TX) # NMPSTCAM_NIC = 16 # NIC MPS TCAM Entries (NPORTS*4) # NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ) # # NVI_OFLD = 0 # Offload uses NIC function to access ports # NFLIQ_OFLD = 16 # Offload Ingress Queues with Free Lists # NETHCTRL_OFLD = 0 # Offload Ethernet Control/TX Queues # NEQ_OFLD = 16 # Offload Egress Queues (FL) # NMPSTCAM_OFLD = 0 # Offload MPS TCAM Entries (uses NIC's) # NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ) # # NVI_RDMA = 0 # RDMA uses NIC function to access ports # NFLIQ_RDMA = 4 # RDMA Ingress Queues with Free Lists # NETHCTRL_RDMA = 0 # RDMA Ethernet Control/TX Queues # NEQ_RDMA = 4 # RDMA Egress Queues (FL) # NMPSTCAM_RDMA = 0 # RDMA MPS TCAM Entries (uses NIC's) # NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ) # # NEQ_WD = 128 # Wire Direct TX Queues and FLs # NETHCTRL_WD = 64 # Wire Direct TX Queues # NFLIQ_WD = 64 ` # Wire Direct Ingress Queues with Free Lists # # NVI_ISCSI = 4 # ISCSI access to NPORTS # NFLIQ_ISCSI = 4 # ISCSI Ingress Queues with Free Lists # NETHCTRL_ISCSI = 0 # ISCSI Ethernet Control/TX Queues # NEQ_ISCSI = 4 # ISCSI Egress Queues (FL) # NMPSTCAM_ISCSI = 4 # ISCSI MPS TCAM Entries (NPORTS) # NMSIX_ISCSI = 4 # ISCSI MSI-X Interrupt Vectors (FLIQ) # # NVI_FCOE = 4 # FCOE access to NPORTS # NFLIQ_FCOE = 34 # FCOE Ingress Queues with Free Lists # NETHCTRL_FCOE = 32 # FCOE Ethernet Control/TX Queues # NEQ_FCOE = 66 # FCOE Egress Queues (FL) # NMPSTCAM_FCOE = 32 # FCOE MPS TCAM Entries (NPORTS) # NMSIX_FCOE = 34 # FCOE MSI-X Interrupt Vectors (FLIQ) # Two extra Ingress Queues per function for Firmware Events and Forwarded # Interrupts, and two extra interrupts per function for Firmware Events (or a # Forwarded Interrupt Queue) and General Interrupts per function. # # NFLIQ_EXTRA = 6 # "extra" Ingress Queues 2*NFUNCS (Firmware and # # Forwarded Interrupts # NMSIX_EXTRA = 6 # extra interrupts 2*NFUNCS (Firmware and # # General Interrupts # Microsoft HyperV resources. The HyperV Virtual Ingress Queues will have # their interrupts forwarded to another set of Forwarded Interrupt Queues. # # NVI_HYPERV = 16 # VMs we want to support # NVIIQ_HYPERV = 2 # Virtual Ingress Queues with Free Lists per VM # NFLIQ_HYPERV = 40 # VIQs + NCPUS Forwarded Interrupt Queues # NEQ_HYPERV = 32 # VIQs Free Lists # NMPSTCAM_HYPERV = 16 # MPS TCAM Entries (NVI_HYPERV) # NMSIX_HYPERV = 8 # NCPUS Forwarded Interrupt Queues # Adding all of the above Unified PF resource needs together: (NIC + OFLD + # RDMA + ISCSI + FCOE + EXTRA + HYPERV) # # NVI_UNIFIED = 28 # NFLIQ_UNIFIED = 106 # NETHCTRL_UNIFIED = 32 # NEQ_UNIFIED = 124 # NMPSTCAM_UNIFIED = 40 # # The sum of all the MSI-X resources above is 74 MSI-X Vectors but we'll round # that up to 128 to make sure the Unified PF doesn't run out of resources. # # NMSIX_UNIFIED = 128 # # The Storage PFs could need up to NPORTS*NCPUS + NMSIX_EXTRA MSI-X Vectors # which is 34 but they're probably safe with 32. # # NMSIX_STORAGE = 32 # Note: The UnifiedPF is PF4 which doesn't have any Virtual Functions # associated with it. Thus, the MSI-X Vector allocations we give to the # UnifiedPF aren't inherited by any Virtual Functions. As a result we can # provision many more Virtual Functions than we can if the UnifiedPF were # one of PF0-3. # # All of the below PCI-E parameters are actually stored in various *_init.txt # files. We include them below essentially as comments. # # For PF0-3 we assign 8 vectors each for NIC Ingress Queues of the associated # ports 0-3. # # For PF4, the Unified PF, we give it an MSI-X Table Size as outlined above. # # For PF5-6 we assign enough MSI-X Vectors to support FCoE and iSCSI # storage applications across all four possible ports. # # Additionally, since the UnifiedPF isn't one of the per-port Physical # Functions, we give the UnifiedPF and the PF0-3 Physical Functions # different PCI Device IDs which will allow Unified and Per-Port Drivers # to directly select the type of Physical Function to which they wish to be # attached. # # Note that the actual values used for the PCI-E Intelectual Property will be # 1 less than those below since that's the way it "counts" things. For # readability, we use the number we actually mean ... # # PF0_INT = 8 # NCPUS # PF1_INT = 8 # NCPUS # PF2_INT = 8 # NCPUS # PF3_INT = 8 # NCPUS # PF0_3_INT = 32 # PF0_INT + PF1_INT + PF2_INT + PF3_INT # # PF4_INT = 128 # NMSIX_UNIFIED # PF5_INT = 32 # NMSIX_STORAGE # PF6_INT = 32 # NMSIX_STORAGE # PF7_INT = 0 # Nothing Assigned # PF4_7_INT = 192 # PF4_INT + PF5_INT + PF6_INT + PF7_INT # # PF0_7_INT = 224 # PF0_3_INT + PF4_7_INT # # With the above we can get 17 VFs/PF0-3 (limited by 336 MPS TCAM entries) # but we'll lower that to 16 to make our total 64 and a nice power of 2 ... # # NVF = 16 # Some OS Drivers manage all application functions for all ports via PF4. # Thus we need to provide a large number of resources here. For Egress # Queues we need to account for both TX Queues as well as Free List Queues # (because the host is responsible for producing Free List Buffers for the # hardware to consume). # [function "4"] wx_caps = all # write/execute permissions for all commands r_caps = all # read permissions for all commands nvi = 34 # NVI_UNIFIED rssnsecret = 16 # all 16 table entries to PF 4 rssnvi = 32 niqflint = 170 # NFLIQ_UNIFIED + NLFIQ_WD nethctrl = 100 # NETHCTRL_UNIFIED + NETHCTRL_WD neq = 256 # NEQ_UNIFIED + NEQ_WD nexactf = 128 # NMPSTCAM_UNIFIED nqpcq = 12288 cmask = all # access to all channels pmask = all # access to all four ports ... nclip = 32 # number of clip region entries nfilter = 368 # number of filter region entries nserver = 128 # number of server region entries nhash = 14336 # number of hash region entries protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu tp_l2t = 4096 tp_ddp = 1 tp_ddp_iscsi = 1 tp_stag = 5 tp_pbl = 34 tp_rq = 10 [function "6"] wx_caps = all # write/execute permissions for all commands r_caps = all # read permissions for all commands nvi = 4 # NPORTS niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA nethctrl = 32 # NPORTS*NCPUS neq = 66 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) + 2 (EXTRA) nexactf = 32 # NPORTS + adding 28 exact entries for FCoE # which is OK since < MIN(SUM PF0..3, PF4) # and we never load PF0..3 and PF4 concurrently cmask = all # access to all channels pmask = all # access to all four ports ... nhash = 2048 tp_l2t = 4 protocol = fcoe_initiator tp_ddp = 2 fcoe_nfcf = 16 fcoe_nvnp = 32 fcoe_nssn = 1024 # The following function, 1023, is not an actual PCIE function but is used to # configure and reserve firmware internal resources that come from the global # resource pool. # [function "1023"] wx_caps = all # write/execute permissions for all commands r_caps = all # read permissions for all commands nvi = 4 # NVI_UNIFIED cmask = all # access to all channels pmask = all # access to all four ports ... nexactf = 8 # NPORTS + DCBX + nfilter = 16 # number of filter region entries # For Virtual functions, we only allow NIC functionality and we only allow # access to one port (1 << PF). Note that because of limitations in the # Scatter Gather Engine (SGE) hardware which checks writes to VF KDOORBELL # and GTS registers, the number of Ingress and Egress Queues must be a power # of 2. # [function "0/*"] # NVF nvi = 1 # 1 port rssnvi = 0 [function "1/*"] # NVF nvi = 1 # 1 port rssnvi = 0 [function "2/*"] # NVF nvi = 1 # 1 port rssnvi = 0 [function "3/*"] # NVF nvi = 1 # 1 port rssnvi = 0 [function "4/*"] # NVF wx_caps = 0x82 # DMAQ | VF r_caps = 0x86 # DMAQ | VF | PORT nvi = 1 # 1 port rssnvi = 1 niqflint = 11 # 8 "Queue Sets" + CIQ + FWEVTQ + FWDINTRQ nethctrl = 8 # 8 "Queue Sets" neq = 16 # 8 "Queue Sets" * 2 nexactf = 4 cmask = all # access to all channels pmask = all # access to all ports nqpcq = 78 protocol = ofld, rdmac # MPS features a 196608 bytes ingress buffer that is used for ingress buffering # for packets from the wire as well as the loopback path of the L2 switch. The # folling params control how the buffer memory is distributed and the L2 flow # control settings: # # bg_mem: %-age of mem to use for port/buffer group # lpbk_mem: %-age of port/bg mem to use for loopback # hwm: high watermark; bytes available when starting to send pause # frames (in units of 0.1 MTU) # lwm: low watermark; bytes remaining when sending 'unpause' frame # (in inuits of 0.1 MTU) # dwm: minimum delta between high and low watermark (in units of 100 # Bytes) # [port "0"] dcb = ppp, dcbx # configure for DCB PPP and enable DCBX offload dcb_dcbx_protocol = auto bg_mem = 25 lpbk_mem = 25 hwm = 30 lwm = 15 dwm = 30 dcb_app_tlv[0] = 0x8906, ethertype, 3 dcb_app_tlv[1] = 0x8914, ethertype, 3 dcb_app_tlv[2] = 3260, socketnum, 5 [port "1"] dcb = ppp, dcbx dcb_dcbx_protocol = auto bg_mem = 25 lpbk_mem = 25 hwm = 30 lwm = 15 dwm = 30 dcb_app_tlv[0] = 0x8906, ethertype, 3 dcb_app_tlv[1] = 0x8914, ethertype, 3 dcb_app_tlv[2] = 3260, socketnum, 5 [port "2"] dcb = ppp, dcbx dcb_dcbx_protocol = auto bg_mem = 25 lpbk_mem = 25 hwm = 30 lwm = 15 dwm = 30 dcb_app_tlv[0] = 0x8906, ethertype, 3 dcb_app_tlv[1] = 0x8914, ethertype, 3 dcb_app_tlv[2] = 3260, socketnum, 5 [port "3"] dcb = ppp, dcbx dcb_dcbx_protocol = auto bg_mem = 25 lpbk_mem = 25 hwm = 30 lwm = 15 dwm = 30 dcb_app_tlv[0] = 0x8906, ethertype, 3 dcb_app_tlv[1] = 0x8914, ethertype, 3 dcb_app_tlv[2] = 3260, socketnum, 5 [fini] version = 0x08000025 checksum = 0xd24280b8 # Total resources used by above allocations: # Virtual Interfaces: 104 # Ingress Queues/w Free Lists and Interrupts: 526 # Egress Queues: 702 # MPS TCAM Entries: 336 # MSI-X Vectors: 736 # Virtual Functions: 64 @FlHH\$WH HHHHH\$0H _HHtH2-+H;t HHù)11X02021*221h2r2112142J2t1V1@1StorPortInitializeStorPortGetPhysicalAddressStorPortGetUncachedExtensionStorPortNotificationstorport.sysDbgPrintKeStallExecutionProcessorKeQueryTimeIncrement_vsnprintfntoskrnl.exeHAL.DLL memcpy_s strcmp StorPortGetBusData-StorPortSetBusDataByOffsetisspaceExAllocatePoolWithTagExFreePoolWithTag0 H`@4VS_VERSION_INFO d @'?StringFileInfo040904B0NCompanyNameChelsio Communicationsh FileDescriptionChelsio iSCSI Crash Dump Driver6 FileVersion6.11.4.100: InternalNamecht4dx64.sys>LegalCopyrightCopyright 2016 Chelsio Communications. All rights reserved.B OriginalFilenamecht4dx64.sys~/ProductNameChelsio Communications iSCSI Crash Dump DriverFProductVersion10.0.10011.16384DVarFileInfo$Translation h `hpxP8Xx8Xxة8Xxت8Xxث8Xxج8Xxح8Xxخ8Xxد`8Xxؠ8XxXxȢآ8Xxأ(HXؤ8Xx8Xxئ8Xxا8Xxب8Xة8Xxت8Xxث8Xx8Xxح8XخXدp8Xؠ8x8xآXxأ8xؤ8Xxإ8Xxئ8Xxا(8x08@HPX`hpxȩЩة (08@HPX`hpxȪЪت (08@HPX`hpxȫЫث (08@HPX`hpxȬЬج08@HPX`h0%0%$ *H %0%10  `He0\ +7N0L0 +70 010  `He uX8|!0_RdoBwʼ:} 003`B1_o`0  *H  01 0 UUS10U Washington10URedmond10U Microsoft Corporation1.0,U%Microsoft Windows Production PCA 20110 231116192009Z 241114192009Z0p1 0 UUS10U Washington10URedmond10U Microsoft Corporation10UMicrosoft Windows0"0  *H 0 8`gըd\$VL]Ut &GDOCkvGwj,F6+V8-5-uu @,׻%sJTJπمD)̨կC }SBvz5{jo2_z9Hx߬~ܑޢ–[۝+6f}8cEx}6[##ZÈH2u:b?v0r0U%0 +7 +0U«vdL MMU5G030EU>0<:0810U Microsoft Corporation10U 229879+5018250U#0)9ėx͐O|US0WUP0N0LJHFhttp://www.microsoft.com/pkiops/crl/MicWinProPCA2011_2011-10-19.crl%200a+U0S0Q+0Ehttp://www.microsoft.com/pkiops/certs/MicWinProPCA2011_2011-10-19.crt0 U00  *H  5cż#CPᰔ_)/Vtʛy(Uw00 avV0  *H  01 0 UUS10U Washington10URedmond10U Microsoft Corporation1200U)Microsoft Root Certificate Authority 20100 111019184142Z 261019185142Z01 0 UUS10U Washington10URedmond10U Microsoft Corporation1.0,U%Microsoft Windows Production PCA 20110"0  *H 0  . i!i33T ҋ8-|byJ?5 pk6u1ݍp7tF([`#,GgQ'rɹ;S5|'# oFnhttp://www.microsoft.com/pki/certs/MicRooCerAut_2010-06-23.crt0  *H  |qQyn9>\` QfG=*hwLb{Ǻz4KbzJ7-W|=ܸZij:ni!7ށugӓW^)9-Es[zFX^gl5?$5 uVx,Јߺ~,c#!xlX6+̤-@EΊ\k>p* j_Gc 26*pZBYqKW~!<ŹE ŕ]b֠c uw}=EWo3wbY~10001 0 UUS10U Washington10URedmond10U Microsoft Corporation1.0,U%Microsoft Windows Production PCA 20113`B1_o`0  `He0 *H  1  +70 +7 10  +70/ *H  1" 'B!kl$Fֆh0ogskSsu0Z +7 1L0J$"Microsoft Windows" http://www.microsoft.com/windows0  *H x2JTcbGgCХɈݴ&FRl6̶ӂJ1f?&uk S/͂؈ӝP:%Px҂4׀0 uc6L~ix:&xEW_Qye84 T#Rof^f0Oļ1{='}a#$ ΝPUdk4FiKSh%E2 vRxM?&B4uK9a9VH)0% +710 *H 010  `He0Y *H  HD0@ +Y 010  `He >u0]|,˴ V%p$P\sI0E0UnQE! Ў%0U#0]^b]eS5r0_UX0V0TRPNhttp://www.microsoft.com/pkiops/crl/Microsoft%20Time-Stamp%20PCA%202010(1).crl0l+`0^0\+0Phttp://www.microsoft.com/pkiops/certs/Microsoft%20Time-Stamp%20PCA%202010(1).crt0 U00U% 0 +0U0  *H  .Tٲ .frnQ?<kv;l(rfC$S;KKBҙ!rx$x! c!uzjPtqe}LCI^Rx;u+q=4~jNǸ{'M7]վ/=}Azut  adU )-t :VkH[2l=bX}`3\OfSqZ~JZ6gF# w2`}jRDFkvPDq\Q17 8n&S|9azĪri65&dژ;{3[~Rb%j]SVMݼ㑏9,Qpi 6-p15(㴇$ɏ~TUmh;Fz)7EFn20\O,b͹⍈䖬Jq[g`= s}AFu_4 }~ٞE߶r/}_۪~66L+nQsM7t4G|?Lۯ^s=CN39LBh.QFѽjZasg^(v3rק  co 6d[!]_0tعP a65Gk\RQ]%PzlrRą<7?xE^ڏriƮ{>j.00 +70# +7*RdĚhttp://www.microsoft.com/pki/certs/MicRooCerAut_2010-06-23.crt0  *H  U}*,g1$[rKo\>NGdx=139q6?dl|u9m1lѡ"fg:SMݘx6.Vi {jo)n?Hum m#TxSu$Wݟ=heV(U'$@]='@8)üTB  jBRu6as.,k{n?, x鑲[It 쑀=J>f;O2ٖtLrou04zP X@1Q{p( 6ںL 4$5g+ 挙"'B=%tt[jў>~13}{8pDѐȫ::bpcSMmqjU3Xpf0=0ؤ01 0 UUS10U Washington10URedmond10U Microsoft Corporation1-0+U $Microsoft Ireland Operations Limited1&0$U Thales TSS ESN:86DF-4BBC-93351%0#UMicrosoft Time-Stamp Service# 0+6#Ge5| r$0~0|1 0 UUS10U Washington10URedmond10U Microsoft Corporation1&0$UMicrosoft Time-Stamp PCA 20100  *H -0"20240401024546Z20240402024546Z0t0: +Y 1,0*0 -00L0 Z06 +Y 1(0&0  +Y  0 00  *H #f{^Z5QHhv9\EOlJpwlfk~ %g~SXۓ1ɡ *i;o?\N[3Z^c6{b|=FgXDcO1 0 00|1 0 UUS10U Washington10URedmond10U Microsoft Corporation1&0$UMicrosoft Time-Stamp PCA 20103]Wԭ0  `HeJ0 *H  1  *H  0/ *H  1" >O OY\"Ē Cq0 *H  /1000 a-eOx{GY7@iQŏz1cf00~0|1 0 UUS10U Washington10URedmond10U Microsoft Corporation1&0$UMicrosoft Time-Stamp PCA 20103]Wԭ0" {&se Cy<8q()&nT0  *H   H0j_Rz4$ O3LFy>kKӔdo˯y eP8MsݏH?@hawX{\wyp/n]X#$ eq:*~EKsq.bgBf&oق [btO4A{ LT~1:{Q%k3qS}T.hH2`Y&&hۻ0"!T ~[L~1QE^.w苨B_U;Ѕ8AZ2>W~#( ܓ6qGI8.E0 0`cʭGlBIwWKe0Q3O3%m;OSS;O?zO&%:+}Ᵹ yOruw(%|%(377@ۆ"Eg